Among many texts on the broadband multiplexing and switching technologies, a good description on the subject is found in an article entitled "Network, Transport, and Switching Integration for Broadband Communications" by Hui in IEEE Network, March 1989, pp 40-51. The article gives an overall picture of STM and ATM technologies. It also mentions a few criteria which should be taken into consideration in choosing the type of switching and multiplexing format.
Generally, in a broadband packet switching system, the switch core provides high bandwidth interconnect between peripherals. Among many switch core architectures, the input buffered switch, the output buffered switch, and the common (shared) memory switch are popular.
In the input or output buffered switch, there is a memory buffer for each channel located either at the input or the output, and a space switch (crosspoint array switch, self-routing circuit switch etc.) to provide the switching. In the input buffered switch, for each cell period one cell is picked from each buffer and switched through the space switch to an output as defined in the header of the cell. In the output buffered switch, on the other hand, the cell is switched through the space switch and then buffered at the output. Some common difficulties with the input or output buffered scheme, in an ATM or ATM/STM hybrid environment, are how to control a large bandwidth system, deal with input and/or output contention, and deal with multicast on the fly. Queueing at the output, as in the output buffered space switch, improves the performance over the input buffered scheme. This is shown in the article by Karol et al in the IEEE Transactions on Communications, Vol. COM-35, No. 12, December 1987, pp 1347-1356, entitled "Input versus Output Queueing on a Space-Division Packet Switch". As reported in the article, a thorough comparison of input versus output queuing on an N.times.N non-blocking space division packet switch indicates that better performance results with output queuing than with input queuing.
The common memory switch core appears to be more attractive than either of the above schemes because of its very simple control concept, its smaller memory size, and it is generally non-blocking. Unlike the input and output buffered switches, the memory of the common memory switch is shared by (or common to) all the input and output ports. Any cell location in memory can be accessed by any input or output port. In general, the controller of such a switch can direct any input or output port to write or read, respectively, into or from any memory location of the cell buffer. This dynamic allotment and non-blocking access capability lends this common memory switch architecture its name, "shared" or "common" buffer memory switch. U.S. Pat. No. 4,603,416, issued Jul. 29, 1986 (Servel) describes the basics of the common memory switch.
In the input or output buffered switch, where separate memories are used for each channel, sufficient memory must be provided for each channel in order to meet the blocking specifications of the switch. The common memory, on the other hand, does not need to reserve large amounts of memory for low traffic channels and as such needs significantly less total memory to meet the same blocking specification. The controller for the common memory switch can be as simple as a FIFO for each output port where the entries into it are pointers to cells destined to that output.
Among various ways of expansion which have been proposed for the above schemes, one popular approach for expansion for the common memory switch is described in the article by Sakurai et al in IEEE Communications Magazine, January 1991, pp 90-96, entitled "Large-Scale ATM Multistage Switching Network with Shared Buffer Memory Switches". It suggests a matrix of a plurality of unit common memory switch modules arranged in multi-stages. For example, each unit module handles a small number of ports (i.e. 32) and in a matrix, the system can grow to several hundred ports. However, matricing creates new blocking problems which are not easily managed. Expanding the unit module instead, requires a memory array which becomes significantly more difficult to design. On the other hand, with the conventional expansion techniques, the input buffer scheme has typically been restricted by controller complexity and the implementation of switching restrictions (i.e. no two packets from the same source at one time). The output buffer alternative requires a high input bandwidth to handle data from multiple sources.
The present invention attempts to solve the above-mentioned problems associated with the large input buffered switch.